This application claims priority from Korean Patent Application No. 2000-36097, filed on Jun. 28, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to integrated circuit memory devices and, more particularly, to non-volatile integrated circuit memory devices storing and being accessible with multi-state data.
Flash memories have recently been developed for personal computers. In this context, flash memories are advantageous because they are capable of storing and quickly erasing large amounts of information.
Before reading information stored in the cells of a memory device, it is necessary to check the information storing state of a selected cell. Signals required to check the storing state of the selected memory cell are applied to circuits associated with the selected memory cell by use of a decoder circuit. A current or voltage signal indicative of the storing state of the selected memory cell is placed on a bit line. By doing so, the storing state indicative of the programmed information of a memory cell can be found by measuring the obtained current or voltage signal.
When reading information stored in a NAND-type memory device, a selected transistor in a selected string is switched to the ON state. In addition, a voltage higher than that applied to the control gate of the selected memory cell is applied to the control gates of unselected memory cells. As a result, the unselected memory cells have a low equivalent resistance as compared to the selected memory cell. The magnitude of the current flowing through the string from the associated bit line thus depends on the information stored in the selected memory cell of the string. The voltage or current corresponding to the information stored in each selected memory cell is sensed by a sensing circuit e.g., a sense amplifier.
Many schemes have been proposed to increase the information storage capacity of memory devices without a consequent increase in chip size. Conventionally, a memory cell stores a single bit of information. It is technically possible, however, to store at least two bits of information in a single memory cell. When 2 bits of information are stored in a single memory cell, the memory cell is programmed with either xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d or xe2x80x9c11xe2x80x9d. Accordingly, a memory device can store twice the information with the same number of memory cells as compared to a memory device wherein only a single bit is stored in a single memory cell. When storing 2 bits per memory cell, a multi-state memory device is provided wherein the threshold voltage of each memory cell can be programmed to have one of four different values. Because the memory capacity per memory cell is doubled, the chip size can be reduced while providing the same memory capacity. As the number of bits stored per memory cell increases, the data storage capacity of the multi-state memory device increases.
The topology of integrated flash memory devices is becoming denser. As this happens, the amount of current passing through a bit line when a selected memory cell is an on-cell is reduced resulting in a longer developing time for the bit line. Accordingly, a need remains for a multi-bit flash memory device that addresses this and other disadvantages associated with the prior art.